Glossary

The words aether’s pages use, in one or two sentences each. Each entry links to the page that explains it in full. Words shared by the whole RAPTOR family (kernel, sample, manifest, DLPack, …) are in the family glossary.

structure of arrays (SoA)

A layout that stores each component of a batch contiguously (all the x values, then all the y values, …) instead of one record per sample, so neighbouring GPU threads or CPU vector lanes read neighbouring memory.

Chunk

One byte allocation on exactly one device. It frees itself when it goes out of scope, or wraps memory you already own without freeing it. See Memory ownership: Chunk, Array, View.

Array (Python)

The array of import aether: one typed buffer on one device (cpu, pinned or CUDA), shared through the buffer protocol and DLPack. Not the C++ aether::Array. See Arrays in Python: import aether.

View

A lightweight, non-owning handle over memory, indexed like a small tensor as v(component, sample). Building one copies nothing. See Views and Items.

Item

One small, fixed-shape value (a vector or a matrix) that the compiler can keep entirely in a thread’s registers. See Views and Items.

expression template

An expression such as a + b*s that builds a tiny description of the computation instead of computing a temporary vector; the work happens once, when it is assigned. See Expression templates.

host, device

The host is the CPU and its memory; the device is a GPU and its memory. AETHER_DEVICEHOST() marks a function that runs correctly on either. See Host vs device code.

kernel entry point

A function the CPU launches to start many GPU threads at once. In aether it is the exception: most code is written once for both sides. See Host vs device code.

replica, partition

A replica is a copy of the same data on every device in a list (ReplicaSet); a partition slices one view’s samples into non-overlapping blocks, one per device or worker, without copying. See Multi-device residency.

packet, lane

A packet is one CPU vector register holding several values (aether::simd::Packet); each value’s slot in it is a lane. See CPU SIMD backend.

BandedReal

An emulated double-precision value with 53 significand bits built from three ordinary float limbs, for GPUs with little native FP64 throughput. See Banded/emulated real arithmetic.

accumulation plane

A per-sample running total that many producers add into without a data race, from a CUDA kernel or an OpenMP loop with the same call. See Accumulation.

append counter

A shared counter that lets an unknown number of writers each claim the next free slot of one destination array. See Accumulation.

numerics contract

The fixed order and spelling of aether’s arithmetic (fold order, division as one reciprocal, compensated sums, non-finite rules) that every target computes against. See Numerics contract.

language core

The numerics contract written out in a language that cannot compile aether’s C++23 templates, generated and checked against the same reference set. See Numerics contract and Plain-C reference core.